VERILOG DASTURLASH TILI YORDAMIDA DASTURLASH
Keywords:
integral mikrosxema, Verilog HDL File, Assignment, 7 segmentli displey, pinlar, segmentlar.Abstract
Maqolada Quartus II muhitida Verilog HDL dasturlash tili yordamida mantiqiy qurilmalarni dasturlash va boshqarish usullari haqida fikr yuritiladi. Qurilma sifatida Altera Cyclone III 3C16 FPGA ni tanlaymiz. Qurilmaning pinlari va portlarini dastur o‘zgaruvchilariga ulash orqali ularga uzatiluvchi signallarni o‘zgartirish va boshqarish usullari yoritiladi.
References
U.Z.Narziyev, B.X.Boboyeva “FPGA qurilmasida taymer yaratish” International сonference on learning and teaching, Том 1, Номер 9 2022 y.
Нарзиев, У., Ражабов, Б. (2018). Управление возможностями программируемой логической интегральной схемы. Вестник БДУ 2/2018, 40-44.
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Published
2023-06-15
How to Cite
Umidjon , Z. N. (2023). VERILOG DASTURLASH TILI YORDAMIDA DASTURLASH. GOLDEN BRAIN, 1(16), 9–14. Retrieved from https://researchedu.org/index.php/goldenbrain/article/view/3698
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